1. Field
This disclosure relates to generating traffic for testing a network or network device.
2. Description of the Related Art
In many types of communications networks, each message to be sent is divided into portions of fixed or variable length. Each portion may be referred to as a packet, a frame, a cell, a datagram, a data unit, or other unit of information, all of which are referred to herein as packets.
Each packet contains a portion of an original message, commonly called the payload of the packet. The payload of a packet may contain data, or may contain voice or video information. The payload of a packet may also contain network management and control information. In addition, each packet contains identification and routing information, commonly called a packet header. The packets are sent individually over the network through multiple switches or nodes. The packets are reassembled into the message at a final destination using the information contained in the packet headers, before the message is delivered to a target device or end user. At the receiving end, the reassembled message is passed to the end user in a format compatible with the user's equipment.
Communications networks that transmit messages as packets are called packet switched networks. Packet switched networks commonly contain a mesh of transmission paths which intersect at hubs or nodes. At least some of the nodes may include a switching device or router that receives packets arriving at the node and retransmits the packets along appropriate outgoing paths. Packet switched networks are governed by a layered structure of industry-standard protocols. Layers 1, 2, and 3 of the structure are the physical layer, the data link layer, and the network layer, respectively.
Layer 1 protocols define the physical (electrical, optical, or wireless) interface between nodes of the network. Layer 1 protocols include various Ethernet physical configurations, the Synchronous Optical Network (SONET) and other optical connection protocols, and various wireless protocols such as WiFi.
Layer 2 protocols govern how data is logically transferred between nodes of the network. Layer 2 protocols include the Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, and Point to Point Protocol (PPP).
Layer 3 protocols govern how packets are routed from a source to a destination along paths connecting multiple nodes of the network. The dominant layer 3 protocols are the well-known Internet Protocol version 4 (IPv4) and version 6 (IPv6). A packet switched network may need to route IP packets using a mixture of the Ethernet, ATM, FR, and/or PPP layer 2 protocols. At least some of the nodes of the network may include a router that extracts a destination address from a network layer header contained within each packet. The router then used the destination address to determine the route or path along which the packet should be retransmitted. A typical packet may pass through a plurality of routers, each of which repeats the actions of extracting the destination address and determining the route or path along which the packet should be retransmitted.
In order to test a packet switched network or a device included in a packet switched communications network, test traffic comprising a large number of packets may be generated, transmitted into the network at one or more ports, and received at different ports. Each packet in the test traffic may be a unicast packet intended for reception at a specific destination port or a multicast packet, which may be intended for reception at two or more destination ports. In this context, the term “port” refers to a communications connection between the network and the equipment used to test the network. The term “port unit” refers to a module within the network test equipment that connects to the network at a port. The received test traffic may be analyzed to measure the performance of the network. Each port unit connected to the network may be both a source of test traffic and a destination for test traffic. Each port unit may emulate a plurality of logical source or destination addresses. The number of port units and the communications paths that connect the port units to the network are typically fixed for the duration of a test session. The internal structure of the network may change during a test session, for example due to failure of a communications path or hardware device.
A series of packets originating from a single port unit and having a specific type of packet and a specific rate will be referred to herein as a “stream.” A source port unit may support multiple outgoing streams simultaneously and concurrently, for example to accommodate multiple packet types, rates, or destinations. “Simultaneously” means “at exactly the same time.” “Concurrently” means “within the same time.”
Within this description, the term “engine” means a collection of hardware, which may be augmented by firmware and/or software, which performs the described functions. An engine may typically be designed using a hardware description language (HDL) that defines the engine primarily in functional terms. The HDL design may be verified using an HDL simulation tool. The verified HDL design may then be converted into a gate netlist or other physical description of the engine in a process commonly termed “synthesis”. The synthesis may be performed automatically using a synthesis tool. The gate netlist or other physical description may be further converted into programming code for implementing the engine in a programmable semiconductor device such as a field programmable gate array (FPGA), a programmable logic device (PLD), a programmable logic arrays (PLA), or other programmable device. The gate netlist or other physical description may be converted into process instructions and masks for fabricating the engine within an application specific integrated circuit (ASIC).
An “engine” may be given a more descriptive name where appropriate. Within this description, various engines have been given names that include one of the nouns “scheduler”, “distributor”, “builder”, “multiplexer”, “generator”, and “receiver”.
Within this description, the term “logic” also means a collection of hardware that performs a described function, which may be on a smaller scale than an “engine”. “Logic” encompasses combinatorial logic circuits; sequential logic circuits which may include flip-flops, registers and other data propagating elements; and complex sequential logic circuits such as finite-state machines.
Within this description, a “unit” also means a collection of hardware, which may be augmented by firmware and/or software, which may be on a larger scale than an “engine”. For example, a unit may contain multiple engines, some of which may perform similar functions in parallel. The terms “logic”, “engine”, and “unit” do not imply any physical separation or demarcation. All or portions of one or more units and/or engines may be collocated on a common card, such as a network card, or within a common FPGA, ASIC, or other circuit device.
When one or more engine, logic circuit, and/or unit is implemented by a one or more programmable semiconductor devices, programming code may be stored on a computer readable storage medium. The programming code may then be used to configure the programmable device or devices. The storage medium may be, for example, a magnetic medium such as a hard disk, a floppy disk and a magnetic tape; an optical medium such as a compact disk (CD-ROM and CD-RW) and a digital versatile disk (DVD and DVD±RW); a flash memory card; or another physical object for storing data. The term “storage medium” does not encompass transitory media such as propagating waveforms and signals.
Throughout this description, elements appearing in block diagrams are assigned three-digit reference designators, where the most significant digit is the figure number where the element is introduced and the two least significant digits are specific to the element. An element that is not described in conjunction with a block diagram may be presumed to have the same characteristics and function as a previously-described element having the same reference designator.
In block diagrams, arrow-terminated lines may indicate data paths rather than signals. Each data path may be multiple bits in width. For example, each data path may consist of 4, 8, 16, 64, 256, or more parallel connections.